A 1-to-8 demultiplexer with data input D in , address inputs S 0 , S 1 , S 2 (with S 0 as the LSB) and $${\overline {\text{Y}} _0}$$ to $${\overline {\text{Y}} _7}$$ as the eight demultiplexed outputs, is to be designed using two 2-to-4 decoders (with enable input $$\overline {\text{E}} $$ and address inputs A 0 and A 1 ) as shown in the figure D in , S 0 , S 1 and S 2 are to be connected to P, Q, R and S, but not necessarily in this order. The respective input connections to P, Q, R and S terminals should be

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